Trap layer substrate stacking technique to improve performance for RF devices

ABSTRACT

Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

REFERENCE TO RELATED APPLICATIONS

This Application is a Continuation of U.S. application Ser. No.15/696,532, filed on Sep. 6, 2017, which is a Divisional of U.S.application Ser. No. 15/051,197, filed on Feb. 23, 2016 (now U.S. Pat.No. 9,761,546, issued on Sep. 12, 2017), which claims the benefit ofU.S. Provisional Application No. 62/243,442, filed on Oct. 19, 2015. Thecontents of the above-referenced Patent Applications are herebyincorporated by reference in their entirety.

BACKGROUND

Integrated circuits are formed on semiconductor substrates and arepackaged to form so-called chips or microchips. Traditionally,integrated circuits are formed on bulk semiconductor substratescomprising semiconductor material, such as silicon. In more recentyears, semiconductor-on-insulator (SOI) substrates have emerged as analternative. SOI substrates have a thin layer of active semiconductor(e.g., silicon) separated from an underlying handle substrate by a layerof insulating material. The layer of insulating material electricallyisolates the thin layer of active semiconductor from the handlesubstrate, thereby reducing current leakage of devices formed within thethin layer of active semiconductor. The thin layer of activesemiconductor also provides for other advantages, such as fasterswitching times and lower operating voltages, which have made SOIsubstrates widely used for high volume fabrication of radio frequency(RF) systems, such as RF switches.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1A illustrates a cross-sectional view of some embodiments of adevice according to some aspects of the present disclosure.

FIG. 1B illustrates an enlarged cross-sectional view of a portion ofFIG. 1A in accordance with some embodiments.

FIGS. 2-13 illustrate some embodiments of cross-sectional views showinga method of forming an IC at various stages of manufacture.

FIG. 14 illustrates a flow diagram of some embodiments of a method offorming a device in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

RF semiconductor devices, which are typically manufactured onsemiconductor-on-insulator (SOI) substrates, operate at high frequenciesand generate RF signals. For these RF devices, the SOI substratestypically include a high-resistance handle substrate, an insulatinglayer over the handle substrate, and a semiconductor layer disposed overthe insulating layer. The high-resistance handle substrate has alow-doping concentration and can exhibit a resistance ranging from 2kilo-ohms-centimeter (kΩ-cm) to 8 kΩ-cm, for example. The highresistance of the handle substrate may improve radio frequency (RF)performance of the RF devices in some regards, but an appreciation inthe present disclosure lies in the fact that the high resistance handlesubstrate may still be a source of Eddy currents when carriers are freedfrom the lattice of the high-resistance handle substrate by the RFsignals. These Eddy currents, which can exhibit high frequencies, are asource of noise in the final chip. In particular, these Eddy currentscan lead to device cross-talk and/or non-linear signal distortion.

To prevent such cross-talk and non-linear signal distortion, the presentdisclosure proposes to manufacture the RF devices on an SOI substrate,which includes a handle substrate, a layer of insulating material, andan active semiconductor layer. However, rather than leaving the handlesubstrate present in the final device, the manufacturing process removesthe handle substrate from the underside of the insulating layer prior tofinal packaging of the device, such that the handle substrate is nolonger present to act as a source of Eddy currents.

With reference to FIG. 1A, a cross-sectional view of some embodiments ofa device 100 according to the present disclosure is provided. The device100 includes a first substrate 106, an interconnect structure 112disposed over the first substrate 106, and a second substrate 122disposed over the interconnect structure 112. The first substrate 106includes an insulating layer 110 and an active semiconductor layer 108;and the interconnect structure 112 includes a plurality of metal layers(e.g., 114 a-114 e) disposed within a dielectric structure 116. One ormore active components such as metal oxide semiconductor field effecttransistors (MOSFETs) 111 are disposed in or over a transistor region102 of the first substrate 106, and one or more passive components suchas inductor 128, capacitor 130, and/or resistor 131 are disposed over anRF region 104 of the first substrate 106. A through-substrate-via (TSV)118 extends vertically through the semiconductor layer 108 and throughthe insulating layer 110. The TSV 118 electrically couples a metal layer(e.g., 114 a, 114 b, 114 c, . . . ) to a contact pad 120 on a lowersurface of the insulating layer 110. A surface of the contact pad 120can remain exposed through a packaging or molding layer 121, therebyallowing the device 100 to be mounted to a circuit board or another chipvia solder bumps, wire bonds, etc., such that the circuit board or otherchip can be electrically coupled to active and/or passive components onthe device 100.

Notably, the first substrate 106 exhibits an absence of a handlesubstrate under the insulating layer 110, and thus the contact pad 120is in direct contact with the lower surface of the insulating layer 110in some embodiments. As will be appreciated in more detail below, forexample with regards to FIGS. 2-13, the device 100 can be manufacturedby a process in which the first substrate 106 is initially an SOI waferwhich includes semiconductor layer 108, insulating layer 110, and ahandle substrate under the insulating layer 110. However, in the finaldevice such as shown in FIG. 1A, the underlying handle substrate hasbeen removed to prevent the underlying handle substrate from acting asan Eddy current source during device operation. Because the insulatinglayer 110 is insulating (and thus not susceptible to Eddy currents),removal of the underlying handle substrate removes a source ofproblematic Eddy currents from the bottom of first substrate 106. Thus,the device 100 can exhibit less cross-talk and less distortion thanconventional devices.

To offset the diminished thickness and structural rigidity of the firstsubstrate 106 due to the removal of the underlying handle substrate, andto provide for sufficient thickness to adequately fill out a package andto provide for structural support during manufacture, a handle substrate124 is disposed over an upper surface 112 u of the interconnectstructure 112. An optional but advantageous trapping layer 126 canseparate the interconnect structure 112 from the handle substrate 124.The trapping layer 126 is configured to trap carriers excited by RFcomponents (e.g., inductor 128 and/or capacitor 130) to limit Eddycurrents in the handle substrate 124. For example, consider a casewhere, when a suitable bias is applied, the inductor 128 and/orcapacitor 130 individually or collectively generate an RF signal, whichcan excite carriers in the handle substrate 124 to some extent. Thetrapping layer 126 is configured to trap these carriers to limitcorresponding Eddy currents. The trapping layer 126 can manifest asdoped or un-doped polysilicon in some embodiments, or can manifest as anamorphous silicon layer. The trapping layer 126 can meet the handlesubstrate 124 at an interface surface that exhibits peaks and valleys insome cases, is substantially planar in other cases, or is generallyroughened in other cases.

FIG. 1B shows some embodiments where the trapping layer 126 is made ofpolysilicon and has a plurality of grain boundaries 132. The grainboundaries 132 are dislocations or defects where the atoms of thetrapping layer 126 are out of position or misaligned within the crystallattice. The grain boundaries 132 act as recombination centers that areconfigured to trap carriers (e.g., carriers from within the handlesubstrate 124). Once trapped within the recombination centers, thelifetime of the carriers is decreased. Therefore, by trapping carrierswithin the grain boundaries 132 of the trapping layer 126, the build-upof carriers along a lower surface of the handle substrate 124 is reducedsubstantially, which mitigates Eddy currents, cross talk, and non-lineardistortion during operation of device 100.

In some embodiments, an interface between the handle substrate 124 andthe trapping layer 126 comprises a series of peaks 134 and valleys 136,which may establish a saw-toothed profile. The peaks 134 and valleys 136facilitate smaller grain sizes, and therefore facilitate more grainboundaries near the top surface of handle substrate 124. Thus, most ofthe carriers are trapped at the grain boundaries 132 to mitigate and/orprevent Eddy currents. The peaks 134 and/or valleys 136 can betriangular-shaped, pyramid-shaped, or cone-shaped, among others. In someembodiments, the peaks 134 can have a height, h, ranging fromapproximately 10 nm to approximately 1 um as measured from the base of aneighboring valley (or a more distant valley), and being approximately0.5 um in some embodiments. The peaks 134 can also have a width, w,ranging from approximately 10 nm to approximately 10 um, and beingapproximately 1 um in some embodiments. In other embodiments, ratherthan being flat-topped as illustrated, the peaks 134 may come to a pointand/or may be rounded. Similarly, rather than coming to a point asillustrated, the valleys 136 can be flat-bottomed or rounded in otherembodiments. In some embodiments, neighboring peaks may have the sameheights and/or widths as one another (neighboring valleys may also havethe same depths and/or widths as one another), but peaks can also havedifferent heights and/or different widths from one another (and valleyscan have different depths and/or widths) in other embodiments. In somecases, the peaks and/or valleys follow a random distribution of heightsand/or widths, follow a Gaussian distribution of heights and/or widths,or follow some other distribution.

The inclusion of the handle substrate 124 over the interconnectstructure 112 may provide increased structural rigidity to offset thelack of a handle substrate under the insulating layer 110. In addition,the trapping layer 126 may reduce Eddy currents as a potential source ofnoise in the handle substrate 124, and although optional, isadvantageous for many applications.

With reference to FIGS. 2-13, a series of cross-sectional viewscollectively depict a method of manufacturing a device in accordancewith some embodiments.

FIG. 2 illustrates a cross-sectional view of some embodiments of aproviding an SOI substrate 106′. As illustrated by FIG. 2, the SOIsubstrate 106′ is a semiconductor-on-insulator (SOI) substrate, whichincludes a handle substrate 202, an insulating layer 110 disposed overthe handle substrate 202, and a semiconductor layer 108 disposed overthe insulating layer 110. In many instances, the SOI substrate 106′ cantake the form of a disc-like wafer. Such a wafer can have a diameter of1-inch (25 mm); 2-inch (51 mm); 3-inch (76 mm); 4-inch (100 mm); 5-inch(130 mm) or 125 mm (4.9 inch); 150 mm (5.9 inch, usually referred to as“6 inch”); 200 mm (7.9 inch, usually referred to as “8 inch”); 300 mm(11.8 inch, usually referred to as “12 inch”); or 450 mm (17.7 inch,usually referred to as “18 inch”); for example.

The handle substrate 202 can have a thickness that is sufficient toprovide the SOI substrate 106′ with sufficient structural rigidity towithstand semiconductor processing operations. For example, in someembodiments the handle substrate 202 has a thickness ranging fromapproximately 200 μm to approximately 1000 μm, being approximately 700μm in some embodiments. In exemplary embodiments, the handle substrate202 can be a low resistivity silicon handle substrate, having aresistance of ranging between several ohm-cm and several tens of ohm-cm,and ranging between 8 ohm-cm and 12 ohm-cm in some embodiments. Inalternative embodiments, the handle substrate 202 can be ahigh-resistance silicon handle substrate, having a resistance betweenseveral hundreds and several thousands of ohms-cm, and ranging betweenfrom 2 kΩ-cm to 8 kΩ-cm in some embodiments. Although either ahigh-resistance or low-resistance silicon substrate can be used, it isadvantageous to use low-resistance silicon substrates becauselow-resistance silicon substrates are cheaper, and since the handlesubstrate 202 will be removed in this manufacturing process, theirgreater resistivity does not provide significant advantages. Otherhandle substrates, such as sapphire substrates, can also be used.

In some embodiments, the insulating layer 110 can have a thicknessranging from less than a micron to several microns, which is sufficientto provide electrical isolation between the handle substrate 202 and thesemiconductor layer 108. In some embodiments, the insulating layer 110can be silicon dioxide, which has a dielectric constant of approximately3.9. In other embodiments, the insulating layer 110 can be a low-κdielectric material. Non-limiting examples of low-κ dielectric materialinclude, but are not limited to: fluorine doped silicon dioxide,carbon-doped silicon dioxide, porous silicon dioxide, porouscarbon-doped silicon dioxide, spin-on organic polymeric dielectrics,and/or spin-on silicon based polymeric dielectric.

In some embodiments, the semiconductor layer 108 is a layer of puresilicon, which can be exhibit a monocrystalline lattice structure andwhich can be intrinsic (e.g., undoped) or doped p-type or n-type. Thesemiconductor layer 108 can have a thickness ranging from severalmicrons down to approximately one nanometer in some embodiments. Thesemiconductor layer 108 can also be a semiconductor compound made ofelements from two or more different groups from the periodic table. Theelements can form binary alloys (two elements, e.g., GaAs), ternaryalloys (three elements, e.g., InGaAs or AlGaAs), or quaternary alloys(four elements, e.g., AlInGaP). The semiconductor layer 108 can includedoped regions, epitaxial layers, insulating layers formed in or on thesemiconductor layer, photoresist layers formed in or on thesemiconductor layer, and/or conducting layers formed in or on thesemiconductor layer.

In FIG. 3, active components, such as MOSFETS 111 and/or otherfield-effect transistors (FETs) are formed in or over a transistorregion 102 of the semiconductor layer 108. A shallow trench isolation(STI) region 117 is formed, in which insulating material surrounds anisland of the material of semiconductor layer 108. A gate electrode 123is formed, sidewall spacers 125 are formed on opposing sidewalls of thegate electrode 123, and source/drain regions 119 are formed on oppositesides of the sidewall spacers 125. A gate dielectric 127 separates thegate electrode 123 from a channel region in the semiconductor layerseparating the source/drain regions 119. In some embodiments, the gateelectrode 123 comprises polysilicon or metal, the sidewall spacers 125comprise silicon nitride, and the gate dielectric 127 comprises silicondioxide or a high-K dielectric. Although not illustrated, thetransistors 111 can also take other forms, such as finFET devices,bipolar junction transistors, floating gate transistors, etc. A resistor131, which can be made of polysilicon 135 for example and can beisolated from the semiconductor layer 108 by gate dielectric and/oranother dielectric 129, can be formed in the RF region 104. A dielectriclayer 133 extends over upper surfaces of the gate electrodes 123 andsource/drain regions 119. The dielectric layer 133 may comprise a low-κdielectric material or silicon dioxide.

In FIG. 4, source/drain contacts 150 are formed to provide an ohmicconnection to the source/drain regions 119 through the dielectric layer133, and gate contacts 152 are formed to provide an ohmic connection totop surfaces of the gate electrodes 123. In some embodiments, thesource/drain contacts 150 and/or gate contacts 152 may comprise, forexample, copper, tungsten, aluminum, gold, titanium or titanium nitride.In addition, a through-substrate-via (TSV) 118 is formed. Theillustrated TSV 118 extends downwardly through the dielectric layer 133,through the semiconductor layer 108, and through the insulating layer110. In other embodiments, the TSV 118 can extend downward partially orfully through the handle substrate 202 as well. The TSV 118 can be madeof for example, copper, tungsten, aluminum, gold, titanium or titaniumnitride, and can be made of the same or different material than thesource/drain contacts 150 and/or gate contacts 152. The TSV 118 istypically formed by a separate photomask and/or etch than thesource/drain contacts and/or gate contacts.

As illustrated by FIG. 5, an interconnect structure 112 is formed overthe SOI substrate 106′. The interconnect structure 112 is formed byforming a first dielectric layer 154, such as a low-κ dielectric layer,nitride, or silicon dioxide dielectric layer, and then forming one ormore photoresist masks over the first dielectric layer 154. With aphotoresist mask in place, an etch is carried out to form trenchopenings and/or via openings in the first dielectric layer 154. Metal isthen deposited to fill the openings in the first dielectric layer 154,thereby forming vias and/or metal lines 156 corresponding to a metal 1layer. In some embodiments, copper is used to fill the openings in thefirst dielectric layer 154, such that vias and metal 1 lines are made ofcopper. In embodiments where copper is used, typically the openings arelined with a diffusion barrier layer, then a copper seed layer is formedover the diffusion barrier layer, and an electroplating process is usedbuild up copper to fill the openings. The diffusion barrier layertypically has a high electrical conductivity in order to maintain a goodelectronic contact, while maintaining a low enough copper diffusivity tosufficiently chemically isolate these copper conductor films fromunderlying structures. Cobalt, ruthenium, tantalum, tantalum nitride,indium oxide, tungsten nitride, and titanium nitride are somenon-limiting examples of materials that can be used for the diffusionbarrier layer. After the metal is grown to fill the openings, a chemicalmechanical planarization (CMP) operation is carried out to planarize thefirst metal layer and first dielectric at plane 154 a. A seconddielectric layer 158 is then formed, openings are formed in the seconddielectric layer 158, and metal is deposited to form vias and metal 2lines 160. Additional dielectric and metal layers are formed in thismanner until the interconnect structure 112 is formed. As illustrated inFIG. 5, the interconnect structure 112 can include an RF component suchas inductor 128 and/or capacitor 130, and which is formed over an RFregion 104 of the SOI substrate 106′.

In FIG. 6, a second handle substrate 124′ such as a bulk silicon waferis provided. The second handle substrate 124′ can have a thicknessranging between 300 μm and 1000 μm, being approximately 700 μm in someembodiments. In some embodiments, the second handle substrate 124′ canhave a resistivity that is greater than that of the handle substrate202. For example, in some embodiments, the second handle substrate 124′can have a resistivity ranging between several hundreds and severalthousands of ohms-cm, and ranging between from 2 kΩ-cm to 8 kΩ-cm insome embodiments, which can help reduce Eddy currents in the finaldevice. In some cases, the second handle substrate 124′ is provided forstructural support, and thus can exhibit an absence of device featuresand an absence of interconnect features in some embodiments. In manyinstances, the second handle substrate 124′ can take the form of adisc-like wafer. Such a wafer can have a diameter of 1-inch (25 mm);2-inch (51 mm); 3-inch (76 mm); 4-inch (100 mm); 5-inch (130 mm) or 125mm (4.9 inch); 150 mm (5.9 inch, usually referred to as “6 inch”); 200mm (7.9 inch, usually referred to as “8 inch”); 300 mm (11.8 inch,usually referred to as “12 inch”); or 450 mm (17.7 inch, usuallyreferred to as “18 inch”); for example; and often has the same diameteras the SOI substrate 106′.

In FIG. 7, a top surface of the second handle substrate 124′ is etchedto form peaks 134 and valleys 136. The peaks 134 and valleys 136 arecreated by first using a photo mask (not shown) to define a pattern onthe top surface, and then exposing the top surface to an etchant 702, tomake the top surface rough with peaks and valleys. In other embodiments,the second handle substrate 124′ may be damaged by mechanically damagingthe top surface of the second handle substrate 124′ (e.g.,micro-scratching, abrasive blasting, etc.), or by performing sputtering,a deposition, or self-assembled monolayer. In some embodiments, thepeaks and valleys comprise saw-toothed shaped protrusions andcorresponding indentations, wherein peaks and valleys of the individual“teeth” are spaced at regular intervals or random intervals. In otherembodiments, the peaks and valleys comprise random shaped protrusionshaving different lattice directions and geometries. In some embodiments,the etchant 702 may comprise a dry etchant (e.g., a plasma etchant, anRIE etchant, etc.) or a wet etchant (e.g., hydrofluoric acid).

In FIG. 8, a trapping layer 126 is formed over the peaks 134 and valleys136, such that an interface is established between the trapping layer126 and the second handle substrate 124′. Thus, a second substrate 122is provided. In some embodiments, the trapping layer 126 can be apolycrystalline silicon layer. In other embodiments, the trapping layer126 may comprise amorphous silicon that includes a dopant species. Invarious embodiments, the dopant species may comprise argon (Ar), carbon(C), and/or germanium (Ge). The surface 802 of the trapping layer whichis furthest from the second handle substrate 124′ may be planarized insome cases, by using CMP for example, to make it more suitable forbonding.

In FIG. 9, the SOI substrate 106′ and interconnect structure 112 arebonded to the second substrate 122. This bonding can take one of manyforms, such as fusion bonding, or bonding through epoxy. In someembodiments, an oxide can be formed over the lower surface of trappinglayer 126 prior to bonding, and the oxide on the lower surface oftrapping layer 126 can then be bonded to the upper surface ofinterconnect structure 112 by carrying out an annealing process.

In FIG. 10, the handle substrate 202 is removed. In some embodiments, atwo-stage process is used to remove the handle substrate 202. During afirst stage, a grinding process is used to thin-down the handlesubstrate, for example by a first distance d1. The grinding process canuse a surface that is fairly abrasive and thus grinds down through thedistance d1 of the handle substrate 202 fairly quickly. After thegrinding process is complete, as determined for example by apredetermined time or by performing measurements indicating thepredetermined distance d1 has been removed; a chemical mechanicalplanarization (CMP) operation is carried out to remove a second,remaining amount d2 of the handle substrate 202. The CMP operationtypically uses a polishing pad that is less abrasive then grinding,thereby providing a smoother, more uniform surface then grinding. TheCMP operation can end, for example, after a predetermined time haselapsed, or when measurements indicate the handle substrate 202 has beenfully removed. It will be appreciated that in some embodiments, someamount of thinned handle substrate 202 may be left on the bottom surfaceof the insulating layer 110.

FIG. 11 shows the structure of FIG. 10 after CMP has been carried out.In FIG. 11's example, the lower portion of TSV 118 is exposed.

In FIG. 12, a contact pad 120 has been formed in direct contact withlower portion of the TSV 118. The contact pad 120 is in direct contactwith underside of insulating layer 110 in some embodiments. The contactpad 120 can be made of, for example, copper, tungsten, aluminum, gold,titanium or titanium nitride. In some embodiments, the contact pad 120is made by forming a metal layer on the bottom surface of the insulatinglayer 110, and then patterning the metal layer, for example using aphotolithographic mask and performing etching of the metal layer withthe photolithographic mask in place. Note that FIG. 12 shows severaldifferent TSVs 118, 118 a, 118 b and corresponding contact pads 120, 120a, 120 b, respectively, to highlight some examples. TSV 118 extendsbetween metal 1 layer, dielectric layer 133, semiconductor layer 108,and insulating layer 110; while the second TSV 118 a extends from alower surface of resistor 131 through dielectric 129, semiconductorlayer 108, and insulating layer 110. A third TSV 118 b extends frommetal 2 line through second dielectric layer 158, first dielectric layer154, dielectric layer 133, through semiconductor layer 108, and throughinsulating layer 110.

After formation of the contact pads 120, the structure, which is oftenstill in the shape of a disc-like wafer, can optionally be bonded toother substrates to establish a 3D IC, and can be cut or scribed intoindividual dies or integrated circuits. Then, in FIG. 13, a packaginglayer 121 is formed to cover a lower surface of the insulating layer110. The packaging layer 121 can extend along sidewalls of the device tocover an upper surface of the second handle substrate 122. The packaginglayer 121 can be made of ceramic or a polymer material, for example, andcan protect the device from environment extremes, corrosiveness, dirt,dust, water vapor, etc.

FIG. 14 illustrates a flow diagram of some embodiments of a method 1400for manufacturing a device according to some aspects of this disclosure.While the disclosed method 1400 is illustrated and described below as aseries of acts or events, it will be appreciated that the illustratedordering of such acts or events are not to be interpreted in a limitingsense. For example, some acts may occur in different orders and/orconcurrently with other acts or events apart from those illustratedand/or described herein. In addition, not all illustrated acts may berequired to implement one or more aspects or embodiments of thedescription herein. Further, one or more of the acts depicted herein maybe carried out in one or more separate acts and/or phases. Further,although FIG. 14 is described in relation to FIGS. 2-13 for clarity, itwill be appreciated that the structures disclosed in FIGS. 2-13 are notlimited to the method of FIG. 14, but instead may stand alone asstructures independent of the method. Similarly, although the method ofFIG. 14 is described in relation to FIGS. 2-13, it will be appreciatedthat the method is not limited to the structures disclosed in FIGS.2-13, but instead may stand alone independent of the structuresdisclosed in FIGS. 2-13.

At 1402, an SOI substrate is provided. The first substrate includes afirst handle substrate, an insulating layer disposed over the firsthandle substrate, and a semiconductor layer disposed over the insulatinglayer. Thus, 1402 can correspond to FIG. 2, for example.

At 1404, an interconnect structure is formed over the SOI substrate. Theinterconnect structure includes a plurality of metal layers disposedwithin a dielectric structure. Thus, 1404 can correspond to FIG. 5, forexample.

At 1406, a second substrate is bonded to an upper surface of theinterconnect structure. In some embodiments, the second substrateincludes a second handle substrate and a trapping layer. In some suchembodiments, after bonding, the trapping layer is disposed between thesecond handle substrate and the upper surface of the interconnectstructure. Thus, 1406 can correspond to FIG. 9, for example.

At 1408, after the second substrate has been bonded to the upper surfaceof the interconnect structure, the first handle substrate is removed toexpose a lower surface of the insulating layer. Thus, 1408 cancorrespond to FIG. 10, for example.

At 1410, after the first handle substrate has been removed, a contactpad is formed in direct contact with the lower surface of the insulatinglayer. A through-substrate-via (TSV) extends vertically through theinsulating layer and semiconductor layer and electrically couples thecontact pad to a metal layer of the interconnect structure. Thus, 1410can correspond to FIG. 12, for example.

Thus, as can be appreciated from above, some embodiments of the presentdisclosure are directed to a device. The device includes a substratecomprising a silicon layer disposed over an insulating layer. Thesubstrate includes a transistor device region and a radio-frequency (RF)region. An interconnect structure is disposed over the substrate andincludes a plurality of metal layers disposed within a dielectricstructure. A handle substrate is disposed over an upper surface of theinterconnect structure. A trapping layer separates the interconnectstructure and the handle substrate.

Other embodiments relate to a method. In the method, a first substrateis provided. The first substrate includes a first handle substrate, aninsulating layer disposed over the first handle substrate, and asemiconductor layer disposed over the insulating layer. An interconnectstructure is formed over the substrate. The interconnect structureincludes a plurality of metal layers disposed within a dielectricstructure. A second substrate, which includes a second handle substrateand a trapping layer, is bonded to an upper surface of the interconnectstructure. After bonding, the trapping layer is disposed between thesecond handle substrate and the upper surface of the interconnectstructure. The second handle substrate is then removed to expose a lowersurface of the insulating layer.

Still other embodiments relate to a method. In this method, an SOIsubstrate is provided. The SOI substrate includes a first handlesubstrate of silicon, an insulating layer disposed over the first handlesubstrate, and a silicon layer disposed over the insulating layer. TheSOI substrate includes a transistor device region and a radio-frequency(RF) region which are spaced laterally apart from one another. Aninterconnect structure is formed over the SOI substrate. Theinterconnect structure includes a plurality of metal layers disposedwithin a dielectric structure. A second substrate, which includes atrapping layer and a second handle substrate made of silicon, is bondedto an upper surface of the interconnect structure. After bonding, thetrapping layer separates the second handle substrate from the uppersurface of the interconnect structure. The first handle substrate isthen removed to expose a lower surface of the insulating layer; and acontact pad is formed in direct contact with a lower surface of theinsulating layer. A through-substrate-via (TSV) extends verticallythrough the silicon layer and through the insulating layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A device, comprising: a substrate comprising asemiconductor layer disposed over an insulating layer; an interconnectstructure disposed over the substrate and including a plurality of metallayers disposed within a dielectric structure; a handle substratedisposed over and spaced apart from an upper surface of the interconnectstructure, the handle substrate including a lower surface comprising aseries of silicon peaks; and a trapping layer of polysilicon materialseparating the interconnect structure and the handle substrate, whereinthe trapping layer has an upper surface comprising first and secondpolysilicon peaks that matingly engage and directly contact the seriesof silicon peaks at an interface; wherein the polysilicon material foreach of the first and second polysilicon peaks has multiple grainboundaries that terminate on the interface for each of the first andsecond polysilicon peaks.
 2. The device of claim 1, further comprising:a contact pad disposed in direct physical contact with a surface of theinsulating layer of the substrate; and a through substrate via extendingthrough the semiconductor layer and the insulating layer andelectrically coupling the contact pad to a metal layer of theinterconnect structure.
 3. The device of claim 1, wherein the handlesubstrate comprises a silicon substrate.
 4. The device of claim 1,wherein a peak has a height ranging from approximately 10 nanometers(nm) to approximately 1 micron and has a width ranging fromapproximately 10 nm to approximately 10 microns.
 5. The device of claim4, wherein a peak is a flat-topped peak.
 6. The device of claim 4,wherein a peak is a rounded peak.
 7. The device of claim 4, whereinneighboring peaks have the same heights and/or widths as one another. 8.The device of claim 4, wherein a peak is triangular-shaped,pyramid-shaped, or cone-shaped.
 9. The device of claim 1, wherein afirst region of the substrate includes a transistor device, and a radiofrequency (RF) device is arranged in the interconnect structure over asecond region of the substrate and is configured to transmit an RFsignal, wherein the trapping layer is configured to trap carriersexcited by the RF signal to limit Eddy currents in the handle substrate.10. The device of claim 1, wherein neighboring peaks have differentheights and/or widths as one another.
 11. The device of claim 1, furthercomprising: a packaging layer covering a lower surface of the insulatinglayer and extending along sidewalls of the device to cover an uppersurface of the handle substrate.
 12. A device, comprising: a firstsubstrate comprising a semiconductor layer disposed over an insulatinglayer; an interconnect structure disposed over the first substrate andincluding a plurality of metal layers disposed within a dielectricstructure; a second substrate disposed over an upper surface of theinterconnect structure; and a charge-trapping layer separating theinterconnect structure and the second substrate, wherein thecharge-trapping layer is made of polysilicon material and meets thesecond substrate at an interface made up of a series of peaks; whereinthe polysilicon material for each of the series of peaks has multiplegrain boundaries that terminate on the interface for each of the seriesof peaks.
 13. The device of claim 12, wherein the series of peaks extenddownwardly from the second substrate into the charge-trapping layer. 14.The device of claim 12, wherein the first substrate includes atransistor region and a radio-frequency (RF) region, wherein the RFregion includes an RF device arranged in the interconnect structure andconfigured to transmit an RF signal, wherein the charge-trapping layeris configured to trap carriers excited by the RF signal to limit Eddycurrents in the second substrate.
 15. The device of claim 12, furthercomprising: a packaging layer covering a lower surface of the insulatinglayer and extending along sidewalls of the device to cover an uppersurface of the second substrate.
 16. The device of claim 12, furthercomprising: a contact pad disposed in direct physical contact with alower surface of the insulating layer of the first substrate; and athrough substrate via extending vertically through the semiconductorlayer and through the insulating layer and electrically coupling thecontact pad to a metal layer of the interconnect structure.
 17. Adevice, comprising: an interconnect structure including a plurality ofmetal layers disposed within a dielectric structure; a substratedisposed over an upper surface of the interconnect structure; and acharge-trapping layer comprising polysilicon material separating theinterconnect structure and the substrate, wherein the charge-trappinglayer meets the substrate at an interface that includes a series ofpeaks extending downwardly from the substrate into an upper surface ofthe charge-trapping layer; wherein the polysilicon material for each ofthe series of peaks has multiple grain boundaries that terminate on theinterface for each of the series of peaks.
 18. The device of claim 17,further comprising: a base substrate comprising a semiconductor layerdisposed over an insulating layer, wherein the base substrate includes atransistor device region and a radio-frequency (RF) region; a contactpad in direct contact with a lower surface of the insulating layer;wherein the interconnect structure is disposed over the base substrateand includes a plurality of metal layers disposed within a dielectricstructure; a through-substrate-via (TSV) extending vertically throughthe semiconductor layer and through the insulating layer to couple ametal layer of the interconnect structure to the contact pad; whereinthe interconnect structure is disposed over the base substrate, andseparates the base substrate from the substrate.
 19. The device of claim18, wherein the substrate has a different ohmic resistance than the basesubstrate.
 20. The device of claim 19, wherein the base substrate has afirst ohmic resistance and the substrate has a second ohmic resistance,the second ohmic resistance being greater than the first ohmicresistance by a factor of ten or more.